MEEP Project: FPGA Shell

A flexible, configurable and portable set of FPGA- IPs that enables any emulated design to communicate with the host and other FPGAs out of the box.

The FPGA shell is meant to be a static perimeter architecture that guarantees that the inside accelerator package can be interchangeable for any other package when meeting a defined I/O interface between the shell and the accelerator package.

The FPGA Shell implements the following interfaces: PCIe: Establishes communication between FPGA and the host server // HBM: High Bandwidth Memory. HBM is the high-performance DRAM interface. It is embedded in the same silicon interposer as the Super Logic Regions (SLR) // Ethernet: 100Gb Ethernet // Aurora: P2P interface // DDR4: External Memory // Info ROM: Stores and reads information on the configuration of the Shell when booting the project // UART