RISC-V SoC Integration

This technology implements a Post-Quantum Cryptographic (PQC) accelerator to integrate it inside a System On Chip (SoC) for FPGA.

Institution:

Institution

Research Group:

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Researcher/s:

Xavier Carril Gil, Juan A. Rodríguez Gracia, Miquel Moretó Planas, Ioannis Vatistas Kostalampros, Carles Hernández Luz, Jordi Ribes González, Oriol Farràs Ventura

RISC-V SoC Integration

Website:

https://dl.acm.org/doi/pdf/10.1145/3675172

Description:

This technology implements a Post-Quantum Cryptographic (PQC) accelerator to integrate it inside a System On Chip (SoC) for FPGA. The module, implemented in a High-Level Synthesis (HLS) approach, accelerates two PQC schemes, the CRYSTALS-Kyber and the CRYSTALS-Dilithium. On the one hand, CRYSTALS-Kyber is a key-encapsulation mechanism (KEM) belonging to asymmetric cryptography. Whose security is based on the difficulty of solving the learning-with-errors (LWE) problem over module lattices. On the other hand, CRYSTALS-DIlithium is a Digital Signature Scheme (DSS). It is strongly secure under chosen message attacks based on the hardness of lattice problems over module lattices. The security notion means that an adversary with access to a signing oracle cannot produce a signature of a message whose signature he hasn't yet seen nor produce a different signature of a message he already saw signed. Then, both schemes (Kyber and Dilithium) are the candidate algorithms to be standardized by the NIST post-quantum cryptography project.

Problem:

N/A

Solution:

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Aplication areas:

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Novelty:

N/A

Protection:

Solderpad Hardware License (Version 0.51)

Target market:

N/A

Keywords:

accelerators, Risc-v

TRL: N/A

CRL: N/A

BRL: N/A

IPRL: N/A

TmRL: N/A

FRL: N/A

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