Lagarto KA

A 2-way, 64-bit superscalar processor with a 12-stage out-of-order microarchitecture based on the RISC-V instruction set.

Institution:

Research Group:

BSC Group: Computer Sciences

Researcher/s:

Abraham Josafat Ruíz Ramírez, Alejandro Iznardo Ruiz, Ansub Zia Taimur, Carlos Rojas Morales, César Alejandro Hernández Calderón, et al.

Description:

Lagarto Ka is a dual-issue, 12-stage out-of-order 64-bit general purpose RISC-V core (RV64GV) that BSC and partners use as the CPU heart of next-gen European SoCs. Because the ISA and RTL are open, the same compiler front-ends and runtime libraries used on incumbert x86/Arm clusters can target Lagarto Ka with only a re-compile -addressing the portable heterogeneous programming model trend. A recently integrated RVV-1.0 vector unit plus AI/HPDA accelerators inside the Kameleon SoC and Intel-3 "TC1" test-chip allow the architecture to push tensors or genomics kernels efficiently.

Value Proposition:

Open RISC-V core enabling European HPC-AI hardware sovereignty

Aplication areas:

Exascale and pre-exascale supercomputers, AI interference engines, genomics alignment, post-quantum cryptography, automotive neural-network co-processors, edge-HPC analytics

Target market:

EuroHPC & national supercomputing centers; Cloud providers diversifying CPU supply chains; Semi-conductor houses building RISC-V accelerator hosts; Automotive & genomics appliance OEMs; Defence/aerospace integrators requiring open, inspectable silicon

Technology Readiness Level (1-9): 3

Protection:

Solderpad Hardware Licence (Version 2.1)

More information

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