Institution:
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High Performance Domain Specific Architectures
Miquel Moretó, Ioannis-Vatistas Kostalampros
This technology is a hardware/software co-design acceleration. The software part is an accelerated version of the purely software implementation of the post-quantum security named Classic McEliece and is being executed at a CPU.
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Possible commercial applications could include the execution of this technology on a heterogeneous System on Chip comprising a CPU and an FPGA device. This SoC could be part of any product that requires post-quantum security protection. Also, the hardware accelerator can be used as a loosely coupled accelerator to the CPU pipeline in order to speed-up the encryption and decryption algorithms of the Classic McEliece Post-Quantum Key Encapsulation Mechanism.
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License (BSD3)
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TRL: 5
CRL: N/A
BRL: N/A
IPRL: N/A
TmRL: N/A
FRL: N/A
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