SafeLS

RISC-V open-source lockstep core based on Frontgrade Gaisler AB's NOEL-V core for the space domain

Institution:

Institution

Research Group:

BSC Group: High-Performance Embedded Systems Lab

Researcher/s:

Marcel Sarraseca Julian, Sergi Alcaide Portet

Description:

SafeLS improves system reliability by duplicating a processor core and running both copies slightly out of sync. Their outputs are continuously compared, and any mismatch triggers a fault alert, enabling early error detection. Its open-source design allows full inspection, supporting certification in safety-critical sectors. It integrates with standard systems and software, so applications run unchanged, ensuring portability. While it simplifies hardware integration, energy use remains higher due to duplication, offering only limited efficiency gains.

Value Proposition:

Open RISC-V lock-step core for certified safety systems

Aplication areas:

Avionics flight computers, automotive ASIL-D ECUs, satellite on-board computers, railway signalling, industrial robotics, nuclear control instrumentation.

Target market:

Aerospace & space primes seeking inspectable processors; Automative Tier-1 suppliers designing RISC-V microcontrollers; Defense contractors demanding sovereign IP; Semiconductors start-ups offering safety SoCs; Certification labs & tooling vendors

Technology Readiness Level (1-9): N/A

Protection:

MIT License

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